1. Field of the Invention
The present invention relates in general to a process for fabricating the memory cell configuration of high-density semiconductor electrically-erasable programmable readonly memory (EEPROM) devices. In particular, the present invention relates to a process for fabricating compact contactless memory arrays on Silicon-On-Insulator (SOI) for flash EEPROM devices. More particularly, the present invention relates to the process of fabrication of the compact contactless flash array on SOI for the flash EEPROM devices and provides for the elimination of the short channel effect during a hot carrier programming phase of the devices.
2. Technical Background
Scaling down of the physical dimensions of the memory cell configuration for semiconductor flash EEPROM devices is indispensable for the upcoming next generation of high-density non-volatile memory devices. In the effort conducted for the scaling down of the basic memory cell units in these flash EEPROM devices, several configurations have been proposed. For example, R. Kirisawa, S. Aritome, R. Nakauama, T. Endoh, R. Shirota and F. Masuoka proposed a NAND structure in their paper "A NAND structured cell with a new programming technology for highly reliable 5-V only flash EEPROM,"1990 Symposium on VLSI Technology, pp. 129-130. This NAND structure does need special design on source and drain regions, which suffer from band-to-band tunneling or even junction breakdown during extraction of electrons out of floating gates. This problem leads to unintentional damage on the thin oxide and difficulty in scaling the sources and drains of flash cells.
On the other hand, B. J. Woo, T. C. Ong, A. Gazio, C. Park, G. Atwood, M. Holler, S. Tam and S. Lai proposed another "FACE" structure in their paper "A novel memory cell using flash array contactless EPROM (FACE) Technology,"1990 IEDM, pp. 90-94. This basic structure, although featuring compact cells for the high-density flash EEPROM devices, does suffer significant short channel effects during the hot carrier programming phase of use. As is well known, short channel effect in memory cell units will easily and likely lead to device punch-through. As device miniaturization technology in semiconductor fabrication advances, this problem represents a serious drawback in the down-scaling of the device memory cells.